Board Layer Stackup Considerations for High Speed Board Design

High-speed designs will only operate successfully when they are built with the right PCB stackup. Your stackup must have the correct arrangement of power and ground planes, with enough layers allocated to signal, and all with material sets and copper selection that can be manufactured at the appropriate scale and cost. If a designer can get the stackup correct, then routing with ensured signal integrity is much easier, and many of the simpler EMI problems will be suppressed or prevented.

To help designers more quickly engineer and build high-speed stackups that support required routing and signal integrity, we've compiled important resources for different classes of high-speed stackups. 

Low Layer Count Stackups

Simpler high-speed PCBs will start as 4-layer boards. My firm view is that 2-layer boards should not be used for designs that will support impedance-controlled high-speed digital interfaces because they cannot guarantee signal integrity or noise control. Any design professional will confirm this point.

The three main types of 4-layer PCB stackups that can support high-speed signals are shown below. Among these stackups, Option 1 is arguably the best choice as provides the most flexibility in routing, and it can be used as a double-sided board. Option 2 can also be used for double-sided placement, but it limits where signals can be routed because there can be crosstalk in the internal layer. Option 3 is good if you have high power requirements, but you can only route high-speed signals on one layer; passives or mechanicals could still be placed on the back layer.

• Learn more about the best 4-layer stackup options for daul-sided PCBs

When higher signal counts are required, such as placing lower-speed signals in an internal layer, the next step is to extend Option 1 to higher layer counts. This would start with a 6-layer stackup, where a dedicated power layer and a signal layer are added into the stackup shown in Option 1 above. This stackup is useful for two reasons:

• Surface layers are good for controlled impedance high-speed interfaces
• Internal layers can support most slower interfaces or control signals
• The power layer can be broken into multiple large rails to support different core voltage levels.

The same procedure can be used to extend the stackup to 8 or more layers with high-speed signals; this type of PCB stackup is discussed in the next section.

• Learn more about 6-layer PCB stackups that can support high-speed PCBs

Moderate Layer Counts

At some point, the board stackup can become so thick that the total PCB thickness will be larger than the standard value. In terms of manufacturing this is not a problem; standard lamination press processes can handle boards beyond the standard thickness value and reaching to multiple mm in thickness. If your goal is a thin board, then you will need thinner layers; options are reinforced PTFE laminates (discussed below) or moving directly to HDI processing.

Moderate layer count boards (above ~8 layers) can tend to have multiple planes layers allocated to power, as well as additional signal layes. For moderate layer count boards, there are few simple guidelines that can help suppress EMI and ensure power integrity:

• It's okay to divide up a power plane into multiple rails as long as signals are not referenced to that plane layer
• If there are multiple power planes, do not stack the power planes on adjacent layers; separate them with a GND plane
• Put fast signals on internal layers between two GND planes; do not reference these to power planes with any splits
• Only use the surface layers for fast microstrips, some power routing if needed, and some GND pour if needed

These guidelines might cause you to add a couple extra layers to your design, but the benefits will be much greater noise control, power integrity, and signal integrity.

More Advanced Stackups

The idea of "more advanced" in the context of high-speed PCB design could mean many things. In high-speed digital designs, it could have two possible meanings in terms of layer selection and arrangement:

• Thin layers to support HDI routing
• High layer counts that force the usage of thin layers
• Routing into fine-pitch BGAs on multiple layers (but not necessarily with HDI)

In other words, you could have very thin signal layers (e.g., 4 mils) with glass-reinforced FR4 with low layer count, or you could have very high layer counts that force the use of thin layers and possibly alternative materials.

The considerations in high-speed layer stackup design for these PCBs focus on required linewidths for components and manufacturability, not simply the Dk and Df values for a stackup. In some cases, a low-Dk, low-Df laminate is needed on signal layers, but not simply because losses are lower. In these designs, manufacturability and signal integrity reign supreme, and thin laminates can be the answer to many challenges in high-speed stackups with high-layer count and/or thin signal layers. Today's main option for thinner boards that can eliminate the need to move to the most advanced processing or HDI processing are reinforced PTFE laminates, which are available in thicknesses below 4 mils.

• Learn more about stackup design for advanced high-speed PCBs

High-Density PCB Stackup Constructions

The most common category of advanced stackups are the various types of high-density stackups, which often mix sub-lamination and sequential lamination buildup processes. These constructions enable a range of high-density designs spanning from PCBs with fine-pitch BGAs to boards with a high density of overlapping SMD components. Within the high-density design category, there are three stackup types:

• Sub-lamination stackup: Uses mechanically drilled blind and buried vias placed within thicker bonded sub-stacks, typically constructed from standard FR4 or high-speed low-loss laminates.
•  Sequential lamination stackup: Uses laser-drilled stacked or staggered microvias built up over a core, typically constructed from thin engineered films such as RCC, BT epoxy, polyimide, or Ajinomoto build-up film.
• Mixed stackup: Combines mechanically drilled blind and buried vias with laser-drilled microvias across multiple bonded sub-stacks, typically constructed from a combination of FR4 and thin HDI buildup materials.

In the case of stackups with HDI buildup layers, some designs incorporate materials that are very thin, low-skew, and laser-drillable. These more advanced stackups support multiple types of high-speed designs, including up to 100G+ data rates involving large digital processors.

Sub-laminations Only

Sub-lamination stackups support high-speed digital designs where thick bonded sub-stacks and mechanically drilled blind and buried vias provide the routing access and via reliability that these systems demand. The first case where this construction is appropriate is PCBs with overlapping BGAs or surface-mount ICs, where the components compete for the same routing channels and the design needs additional inner layers reachable through blind vias to fan out and escape the densely packed pin fields.

The second case is designs that need multiple stubless via transitions, where high-speed nets must move between layers without leaving long resonant stubs that degrade signal integrity at high edge rates. Mechanically drilled blind and buried vias placed within the sub-laminations allow these transitions to terminate cleanly on the intended layers, which removes the stub without forcing a back drill on every high-speed net.

Sub-lamination build with mechanically-drilled blind and buried vias. These stackups can provide a large number of via transitions that may not have stubs (or very small stubs) which is beneficial for high-speed striplines.

Sequential Laminations Only

Sequential lamination stackups support high-density designs that also carry high-speed digital interfaces, using laser-drilled microvias built up over an internal core to reach the routing density these designs require. The first case where this construction is appropriate is PCBs with fine-pitch BGAs or QFNs at 0.5 mm pitch and below, where the pad and via geometry is too small for mechanical drilling and only laser-drilled microvias can satisfy the aspect ratio and capture pad requirements needed to escape the package.

The second case is designs that need multiple stubless via transitions, where stacked or staggered microvias move signals between adjacent buildup layers without producing the long via stubs that would otherwise require back drilling. The thin buildup films used in these stackups also place power and ground planes close together, which increases planar capacitance and lowers PDN inductance for the dense, high-current loads typical of these designs.

HDI stackup with multiple microvia layers.

Designs with microvias are required to support high-density fine-pitch digital processors, most often FPGAs and large CPUs found in servers, high-end computers, and some embedded systems. Despite using microvias, these designs will still use power-ground plane pairs to ensure power integrity in large processors.

Stackups With Mixed Laminations

Stackups with mixed laminations satisfy both sets of goals at once and are often used in high-density designs with overlapping BGAs. These designs normally have high layer counts, but for multiple reasons stacked microvias cannot be used to route deep into the stackup. A blind via is therefore used in a sub-lamination to reach the inner layers. This eliminates the use of a buried core via to complete a transition across the entire stackup, and a through-hole is used instead to connect a transition through a mechanical blind via to the opposite surface layer.

This stackup uses multiple sub-laminations in the core region of the PCB stackup.

An important feature of all these stackups is that they can eliminate back drilling. In boards that only require a small number of back drills, the additional cost is marginal and would not on its own justify one of these more advanced stackups. Many digital designs with a large number of high-speed nets require multiple back drills, so it makes more sense to use a more advanced stackup and gain the advantages provided by these via structures.

The table below summarizes the three high-density stackup constructions and the conditions under which each one is the right choice.

Hybrid PCB Stackups

A hybrid PCB stackup incorporates different material types that would not normally be combined into the same layer stack build. The most common type of hybrid stackup uses FR4 combined with PTFE materials, which may be bonded together with an FR4 prepreg or a PTFE bondply. These stackups are most often used in RF designs operating above 10 GHz that also carry multiple digital interfaces requiring impedance control.

*[Image placeholder: hybrid PCB stackup example]*

Reliability is the main concern with hybrid stackups because combining dissimilar materials introduces several mechanical and process risks during fabrication. The differences in material properties create conditions that standard FR4 processing does not account for, and these conditions directly affect quality and yield. The primary reliability risks to plan for include:

• Slight asymmetry in the stackup caused by thickness differences between the dissimilar laminates, which can drive warpage if the build is not balanced
• Hole wall preparation that differs between PTFE and FR4 materials, which affects hole wall plating consistency through the via barrel
• Mismatched CTE values between PTFE and FR4, which create differential expansion across the stackup and increase the risk of barrel cracking and delamination under thermal cycling
• Drill speeds that vary by material due to differences in mechanical strength, which complicates drilling through mixed material regions

The most effective way to manage these risks is to engineer the stackup with the fabricator early rather than handing over a finished build. A workable approach is to start with materials you have used before, such as Rogers laminates, then send the fabricator a proposed stackup to confirm they can hit the target layer arrangement.

The fabricator returns a buildable structure at the required layer count along with dielectric and impedance data for the hybrid construction, which then becomes the basis for the impedance design rules used during layout and routing. Aim for a symmetric stackup wherever the material constraints allow it, since symmetry reduces warping, and confirm that the fabricator has prior experience processing hybrid designs before committing to the construction.

Full Control Over Your High-Speed PCB Stackup

Altium Designer gives designers full control over the PCB layer stackup inside the Layer Stack Manager. Every parameter that defines the stackup and its materials can be specified directly, which keeps the electrical and mechanical model of the board consistent with what the fabricator will actually build. Inside the Layer Stack Manager, designers can specify:

• Layer count and the ordering of signal, plane, and dielectric layers
• Copper weights (base or finished) on each layer
• Dielectric materials and thicknesses for prepreg and core
• Dielectric constant and loss tangent for each material
• Impedance profiles and the geometry of single-ended and differential controlled-impedance traces

This level of control means the stackup drives impedance calculations, via span definitions, and material assignments from a single source.

Once the stackup is defined, designers can automatically generate stackup diagrams for their master fabrication drawings using Altium Draftsman. The Draftsman environment pulls the stackup data directly from the Layer Stack Manager, so the cross-section drawing, layer table, and material callouts stay synchronized with the design data. When the stackup changes, the documentation updates from the same source, which removes the manual redrawing that introduces errors between the design and the fabrication package handed to the manufacturer.

Other Resources

The other areas of stackup design that are important for high-speed PCBs are power integrity and signal integrity.

There is also the potential need to shift to HDI designs when BGA packages have very fine pitch, and when layers get very thin. Take a look at these resources to learn more about these important areas of PCB design:

• 11 HDI Materials You Need to Know
• 2+N+2 PCB Stackup Design for HDI Boards
• Ebook: PDN Simulation and Analysis Guide
• The Impact of Stackup Design on Signal Integrity

Whether you need to build reliable power electronics or advanced digital systems, Altium Develop unites every discipline into one collaborative force. Free from silos. Free from limits. It’s where engineers, designers, and innovators work as one to create without constraints. Experience Altium Develop today!

Frequently Asked Questions

When should a PCB use a sub-lamination stackup in high-speed PCB design?

Use a sub-lamination stackup when high-speed signals need stubless layer transitions but the design does not require laser-drilled microvias. Mechanically drilled blind and buried vias can reach internal routing layers without leaving long resonant stubs, which is useful for overlapping BGAs, dense SMD placement, and high-speed stripline routing.

How can advanced PCB stackups reduce or eliminate back drilling?

Advanced stackups reduce back drilling by using blind, buried, stacked, or staggered vias that stop on the required routing layers. This removes unused via stubs before they become signal integrity problems on high-speed nets.

Why are hybrid PCB stackups used in RF and high-speed digital designs?

Hybrid stackups are used when one PCB needs both RF material performance and digital routing capability. A common example is PTFE material for RF sections above 10 GHz combined with FR4 layers for controlled-impedance digital interfaces.

What reliability risks occur when FR4 and PTFE are combined in one PCB stackup?

FR4 and PTFE have different mechanical and thermal properties, so hybrid stackups can suffer from warpage, CTE mismatch, plating inconsistency, barrel cracking, and delamination. These risks should be reviewed with the fabricator before layout.