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避免高性能多板 PCB 设计中的跨板信号完整性问题

Adam J. Fleischer
|  已创建：五月 5, 2026
At a Glance

避免多板 PCB 设计中的跨板信号完整性失效。了解连接器过渡、偏斜和边界如何消耗裕量。

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避免高性能多板 PCB 设计中的跨板信号完整性问题

多板系统中的大多数信号完整性问题，都可追溯到边界，而不是它们之间那些阻抗受控的走线。连接器引出、线缆过渡或软硬结合处都会引入阻抗不连续、参考变化和偏斜，这些问题会沿整个通道不断累积。若工程师将每块板都视为彼此孤立的布线问题，并把互连决策留到机械封装阶段，最终就会发现裕量消耗在那些他们从未被明确设计过的边界上。

首要约束是：每一条高速通道都必须作为从发射端到接收端的完整路径来进行预算，其中包括板与板之间、连接器、线缆以及柔性段之间的每一次过渡。当边界归属不清或缺乏文档记录时，各板卡团队都会进行局部优化，却没有人真正负责这些过渡。结果就是，在系统层面上，这条通道无法满足任何一方的阻抗或偏斜预算。

关键要点

  • 跨板信号完整性（SI）失效始于边界。 连接器引出、参考路径中断以及互连过渡会消耗掉每块板看似拥有的链路裕量，最终装配后的通道失效。 
  • 偏斜会在整个系统中叠加。 对于并行接口和差分对：应在每块板上、在你能控制布线的位置以及连接器接口前后维持偏斜，而不是试图在某一块板上一次性补偿所有长度/延迟失配。
  • 了解连接器对高带宽通道的能力。 应基于供应商数据评估连接器，并利用其仿真模型在仿真中全面评估系统性能。

将连接器引出作为可复用的设计模式

大多数 SI 漏网问题发生在过渡处，而不是在长距离且控制良好的走线中间。连接器边界应被视为一种可复用的设计模式，并通过约束和评审关卡加以保护，以便每个板卡团队都遵循相同的假设。当引出区域由一套一致的规则定义，而不是交由个人判断时，同样的性能就能够在不同设计间复用。至少，这种设计模式应强制包含：

  • 接口定义： 标准、目标数据速率、覆盖板卡、连接器、线缆或 柔性段 的拓扑图，以及参考变化。
  • 偏斜预算： 对内偏斜和通道间偏斜，并按各段进行分配。
  • 连接器规则： 引脚映射约束、地引脚交错、扇出布线以及过孔使用。
  • 需要重新检查边界的变更触发条件： 更换连接器、层叠结构变化、线缆长度变化、板卡位置调整，或互连附近的外壳变更。

在这些要素被锁定后，引出区域就成为受约束的设计模块，而不是临时性的布线操作。如果 差分对 在引出处发生换层，则应保持过渡对称：两条线使用相同的过孔结构、相同的扇入/扇出方式，以及相同的层使用方式。





Connector with black and red wire connects to PCB board

影响通道性能的机械约束

堆叠高度、对齐公差、弯折约束和服务布线，都是通道约束，而不只是机械问题。线缆改道若增加 50 mm 长度或改变弯曲半径，就会改变延迟，且可能改变耦合。板卡位置调整若改变了连接器配合高度，则可能改变过孔残桩长度，或需要不同的层叠过渡。

应将这些关系记录在 ICD 中，以便机械变更能够自动触发边界复核。缺少这种联动时，机械团队做出的变更从封装角度看似无害，却会在不知不觉中侵蚀 SI 裕量。

变更类别

示例

对通道的影响

所需操作

连接器/引出

系列替换、引脚映射修订、配合高度变化

阻抗不连续、残桩长度、扇出几何

重新仿真引出、更新 ICD、重新检查偏斜预算

层叠/结构

材料变化、过孔结构修订、背钻决策

阻抗偏移、参考过渡行为

重新运行阻抗和 TDR 模型，验证引出对称性

机械/布线

线缆长度变化、弯曲半径、板卡位置调整

延迟变化、耦合变化、配合几何

重新验证偏斜预算，确认连接器对齐

Retimer/redriver 放置

通道分段变化

新的合规点、损耗预算变化

重新划分通道，更新 ICD 段定义

信号完整性通道建模

要建立完整的通道模型，应从发射端到接收端 级联 S 参数模块。通道中的每个段，包括封装、板上布线、过孔引出、连接器和线缆，都需要特定类型的模型。

  • 对均匀走线使用传输线模型
  • 对不连续点和连接器应用 S 参数模块
  • 将单独的 S 参数转换为 T 矩阵并按顺序相乘
  • 运行合规性仿真（插入损耗、回波损耗、眼图、COM），识别对损耗或反射预算影响最大的关键段
  • 在硬件可用后，结合 TDR 和 VNA 测量进行相关性验证
  • 在互连控制文档中记录所有模型假设（Touchstone 文件、引脚映射、层叠结构、引出几何）
  • 当边界条件变化时，重新生成受影响模型并重新运行仿真

仿真与测量之间的差异，通常可追溯到引出几何差异、连接器波动，或介电特性偏离数据手册数值。迭代时应一次只改变一个变量。若在多个板卡版本中将连接器边界视为固定不变的抽象模型，这是一种极易在不知不觉中侵蚀 SI 裕量的做法，直到原型测量暴露问题时才会发现。

多板设计的系统级 SI 关卡检查清单

布局前

  • 为 
  • 建立互连模型。锁定首次布局迭代所需的连接器方向和配合假设。
  • 指定端到端链路负责人。

布局期间

  • 标准化连接器引出几何：焊盘/过孔结构、反焊盘、缝合以及参考连续性。
  • 控制连接器区域内的过孔残桩。
  • 依据系统预算跟踪偏斜，并避免在引出处进行调节，除非被明确允许。

原型发布前

  • 执行以边界为先的评审：映射、引出、回流路径连续性、偏斜分配以及机械约束。
  • 确认装配后的通道与假定拓扑一致：板卡位置、堆叠高度、线缆或柔性段长度，以及弯折约束。
  • 定义上电调试验证条件：线缆组、夹具和装配变量。

上电调试后

  • 若链路失败，首先审查边界：引脚映射和方向、引出几何、参考连续性以及各段偏斜。
  • 记录所有涉及互连路径的变更，并在触发条件出现时重新执行边界评审。

借助 Altium Agile Teams 保持多板上下文可见

系统级 SI 横跨电气、机械和采购等现实因素。Altium Agile Teams 可在系统演进过程中保持这种多板上下文的可见性，使团队能够在布局和封装决策锁定之前捕捉边界变更。 

设计评审发生在设计上下文中。如果某项机械变更导致连接器位置移动并破坏了通道假设，电气团队能够及早看到。连接器和线缆决策可以结合来自 Octopart 的实时可用性和风险数据一并做出，从而更早锁定那些定义边界的关键器件。变更跟踪始终与设计状态关联，因此连接器替换和层叠结构修订能够被相关干系人及时看到。 

更多详情，请参阅 Altium 关于同步多板装配的文档。这是将多板关系如何被捕获并保持最新这一过程正式化的一个有用后续步骤。 了解更多 Altium Agile Teams →

PCB仿真软件 PCB Design and Simulation Workflows Altium Designer中的SPICE仿真 xSignals in Altium PDN Analyzer for DC Power Integrity How to: Simulation and Analysis Circuit Simulation Documentation

关于作者

关于作者

Adam Fleischer is a principal at etimes.com, a technology marketing consultancy that works with technology leaders – like Microsoft, SAP, IBM, and Arrow Electronics – as well as with small high-growth companies. Adam has been a tech geek since programming a lunar landing game on a DEC mainframe as a kid. Adam founded and for a decade acted as CEO of E.ON Interactive, a boutique award-winning creative interactive design agency in Silicon Valley. He holds an MBA from Stanford’s Graduate School of Business and a B.A. from Columbia University. Adam also has a background in performance magic and is currently on the executive team organizing an international conference on how performance magic inspires creativity in technology and science. 

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