LVDS Routing and the Art of Differential Signaling

One of the early differential signaling protocols used for serial communication was low-voltage differential signaling, or LVDS. Throughout the development of standardized protocols and interfaces, there have been many standards that have come and gone. LVDS started as an excellent general purpose high-speed digital communication standard, and it still sees such use to this day. As a differential communication standard, it brings some signal integrity and EMI benefits as long as certain requirements are met.

This article will provide a basic overview of LVDS routing requirements in a PCB, as well as some innovative use cases of LVDS routing for parallel differential interfaces. If you have never worked with an LVDS interface before, these guidelines will tell you what you need to verify before you create LVDS design rules and route your differential pairs.

Physical Design For LVDS

As a differential interface, LVDS follows the standard set of differential pair design guidelines to ensure signal integrity:

• Design the traces to a target odd-mode impedance
• Prefer to route traces over a uniform ground plane
• Use coupling (AC or DC) where required based on receiver characteristics
• Termination may require an external circuit, depending on the components being used
• Fan-in, fan-out, neck down, and teardrops are all appropriate

Again, LVDS just uses a differential pair linking a driver and receiver; there is no limit on trace width and spacing other than what is manufacturable as long as it meets the differential impedance requirements.

LVDS Architecture

At its core, LVDS consists of a differential transmitter and differential receiver with DC reference voltage, so LVDS measures the difference between non-inverting and inverting signal levels about a common-mode DC offset voltage. This DC offset is 1.2 V (typical for devices powered with 2.5 V, 3.3 V, and 5 V I/O supplies), although some standards like sub-LVDS use a lower 0.9 V offset to ensure compatibility with 1.8 V I/O supplies.

The main LVDS architectural elements include:

• Termination resistor placed in parallel at the receive end of the link to terminate the signal transmission line; this resistor could be integrated into your receiver (e.g., in an FPGA), so check the datasheet
• AC coupling is used to isolate drivers and receivers requiring different common-mode DC offset voltages; if discrete termination is required, then a reference voltage connection is required in the termination circuit
• LVDS transmits binary data at up to 655 Mbps per lane according to the TIA/EIA-644 standard, although the data rates that can be used in practice can be in the Gbps range
• Multiple topologies are available for LVDS, including parallel lanes shared on a driver and receiver for higher data transmission, multi-drop topology with multiple receivers, and multi-point topology (M-LVDS) where a group of drivers and receivers share a physical medium.

LVDS Signal Integrity Facts

In terms of the signal behavior, LVDS uses a +/-175 mV swing about the common-mode DC offset voltage to define logic levels; this low voltage swing is the reason for the protocol's name. The LVDS driver operates with a 3.5 milliamp push-pull mode current source, with each line in the differential pair carrying current in opposite directions. When terminated to the target 100 Ohm impedance, the injected current develops +/-350 mV across the receiver's pins.

A few points to note about signal integrity in an LVDS link:

• LVDS links require a 100 Ohms differential impedance (50 Ohms odd-mode)
• For LVDS links confined to a single PCB, it is best to route them over a ground plane to ensure the trace width and spacing are not too large or small, respectively
• LVDS receivers have a HIGH logic threshold of 100 mV or less, so this allows for at least 6 dB loss budget from PCB traces or cables
• A compliant LVDS receiver will tolerate ground potential offsets of up to +/-1 V between the driver and receiver ground connections
• Placement of AC coupling capacitors is needed when DC offsets need to be changed between driver and receiver
• Make sure to match trace lengths (signal propagation times) within the pair; for parallel LVDS, match the total length/delay of all pairs as well

The ground offset factor is typical of all differential pairs as the interface eliminates the common-mode DC offset voltage, even in the case where offsets are quite large. In terms of LVDS with a 1.2V common-mode DC offset voltage, this means an LVDS receiver can operate within a DC offset ranging from 0.2V to 2.2V. This makes LVDS ideal for applications where driver and receiver may be on different boards with separate power supplies and floating grounds.

LVDS Signal Integrity Myths

As differential pairs with bandwidth reaching only a few GHz, LVDS is quite easy to design and route. Design the link to the required impedance and use a ground plane, and beyond this there is not much else to worry about.

Some myths that should be addressed surrounding the use of LVDS include:

• Routing through vias - Vias on LVDS do not require impedance matching; standard via diameters and standard clearances will not create excess return losses
• Stubs on vias - Through-hole vias with leftover stubs can be used as long as the PCB is not too thick (read more here)
• Straight-line routing - Curved traces or straight-line only traces are not required, you can route with 45 degree angles or even 90 degree angles
• Trace length - There is no maximum trace length in the LVDS standard; as long as the loss budget is obeyed then any trace length could be used
• Trace-to-trace spacing - There is no maximum/minimum spacing requirement between the traces in an LVDS differential pair. As long as you reach the odd-more impedance requirement any spacing can be used
• Routing layers - LVDS can be routed as microstrips or striplines; although microstrips generally have less insertion loss, striplines will still work

The image below shows a Texas Instruments reference design that uses multiple LVDS lanes for communication between a set of RF ASICs and an FPGA. In this example, specialty logic is implemented in the ASIC such that one of these lanes is a clock lane, while the other is a data lane. You'll notice that the traces in each LVDS differential pair are delay-matched to each other as would be expected in a parallel interface.

Example delay-matched LVDS lanes (1x clock, 1x data)

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