How Blind, Buried and Through-Hole Vias Can Impact Your PCB Design

The majority of PCBs produced around the world use through-hole vias to route between layers. Through-hole vias are part of a standard construction process, where the PCB stack-up is laminated with multiple layers and a final drilling process is performed to fabricate these holes. These are then plated to form the conductive through-hole vias that signals use to transit across the stack-up.

PCBs that use blind and buried mechanically drilled vias have changes to their DFM requirements. Although these vias also use a stack, drill, and plate process, multiple rounds of cleaning are possible on a single layer, which may totally change the design and routing approach. In addition, via sizing requirements change when using blind and buried vias. Due to these factors with blind and buried vias, we will discuss some of the important DFM considerations with these vias and how they impact your PCB layout.

Getting Started With DFM or Blind and Buried Vias

Mechanically drilled blind vias carry some basic DFM requirements, and the same requirements can be found in buried vias. First, we have to look at the DFM requirements for blind and buried vias, and then we can see how this impacts DFM for the rest of the PCB.

The basic DFM points surround blind via fabrication with mechanical drilling. When using mechanical drilling, we are using a sub-lamination build process, where sub-stackups are first fabricated and then bonded together using prepregs to construct the entire stack-up. Specifically for the blind and buried vias, we have the following constraints:

• Mechanically drilled hole diameter must be greater than 6 mil
• Drilled hole aspect ratio must not exceed PCB fabricator limits
• Landing pad oversize must comply with annular ring requirements

The last point is important for Class 2 or Class 3 PCBs and PCBAs, which demand some minimum via pad oversize to ensure sufficient annular ring and account for drill wander.

There are additional rules concerning the placement of blind and buried via spans in a PCB stack-up. These constraints relate to manufacturability, as only certain via spans can be fabricated.

• Via spans cannot cross each other, but they can be nested
• One via span cannot end on the same layer that another via span begins
• Sub-laminations must be bonded together using a prepreg
• It is recommended, though not required, that via spans be symmetric across the stack-up

As a result, an optimal sub-lamination build with mechanically drilled blind and buried vias might look like the example stack-up below.

Note how the placement of the via spans drives the usage of core and prepreg in specific locations in the stack-up. This is done to bond the sub-laminations together and is required to create a stack-up that can be manufactured.

Blind and Buried Vias Impact Other Parts of DFM

What often gets lost in these discussions about blind and buried vias is how their usage impacts DFM in other areas of the design. While they provide the convenience of routing, they create trade-offs in other areas of the design which the designer must anticipate. There are two major aspects: copper weight and copper balancing.

Copper Weights Change Due to Plating

When using mechanically drilled blind and buried vias, copper weights on internal layers where via spans begin and end will get plated up during the process of forming the via walls. This increases the copper weight on each layer, which impacts the following constraints in your PCB design rules:

• Etch clearance requirements
• Pad oversize requirements on vias
• Minimum drill diameter and maximum aspect ratio

Remember that the point of using blind vias, including mechanically drilled blind vias, is to allow for higher-density routing and placement. If many via spans are starting or ending on the same layer, this can increase the finished copper weight significantly, and this requires higher etch clearance limits on that layer.

The larger pad oversize and potentially larger drill diameter are also side effects of the higher copper weight when multiple via spans start or end on the same layer. The higher copper weight requires more drilling time and potentially more wander, particularly when the top surface layer is plated up with heavy copper. This will force larger pad oversize as well as large drill diameters in order to comply with the annular ring requirements for IPC Class 2 or Class 3 products.

Copper Weights Need to Be Balanced

Normally, when we refer to copper balancing in a PCB stack-up, we are referring to ensuring a symmetric distribution of copper by flooding specific layers with grounded copper pours. But in this case, we are referring to ensuring the distribution of copper weights is symmetric in the top and bottom halves of the PCB stack-up. In other words, the blind and buried via spans should be mirror images of each other about the central sub-lamination or central dielectric.

These copper thickness values on the various layers can be converted to copper weights. The reason for balancing the copper weights in the PCB stack-up is to prevent warpage. Mismatched copper weights in a stack-up are much more likely to create warpage than mismatched copper pours in a stack-up. This is the major reason we prefer to use symmetric via spans when mechanically drilled blind and buried vias are used in a PCB stack-up.

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