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去耦电容的放置,是 PCB 布局中那种“一个简单规则被反复传播,却早已超出其实际适用条件”的典型话题之一。大家都很熟悉那条标准建议:把电容尽可能靠近电源引脚。设计人员会在数据手册、应用笔记、布局检查清单,甚至 AI 生成的示意图中反复看到这句话——这些图里电容常常像装饰边框一样围着每个 IC 排一圈。问题在于,这条建议把几种不同的 PDN 结构压缩成了一条规则,而这些结构的行为其实并不相同。 一旦明确了电容与负载之间的感性路径,放置决策就会容易得多。在某些板子上,哪怕只是把电容稍微移远一点,路径电感也会增加到足以让这个器件的效果明显变差。而在另一些板子上,尤其是电源层与地层间距很小的多层设计中,电容的具体位置可能就没那么敏感,因为平面本身提供了低电感电流路径。 关于去耦电容放置的背景 围绕去耦电容放置的“破除迷思”讨论,部分可追溯到 Todd Hubing 博士的 IEEE 论文,该论文研究了带有内部电源层和地层的多层 PCB。论文考察了:在采用低电感平面对之后,单面板和双面板上熟悉的放置规则是否依然适用。其核心结论,也是至今仍引发讨论的一点是:当去耦电容连接到紧密间隔的平面(10 mil)上时,只要电容没有放得离负载过远,测得的电源总线阻抗对电容放置位置可能几乎不敏感。 这个结论很有价值,但也很容易被过度泛化。Hubing
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